Tunable voltage margin access diodes

ABSTRACT

The present invention relates generally to high current density access devices (ADs), and more particularly, to a structure and method of forming tunable voltage margin access diodes in phase change memory (PCM) blocks using layers of copper-containing mixed ionic-electronic conduction (MIEC) materials. Embodiments of the present invention may use layers MIEC material to form an access device that can supply high current-densities and operate reliably while being fabricated at temperatures that are compatible with standard BEOL processing. By varying the deposition technique and amount of MIEC material used, the voltage margin (i.e. the voltage at which the device turns on and the current is above the noise floor) of the access device may be tuned to specific operating conditions of different memory devices.

BACKGROUND

The present invention relates generally to high current density access devices, and more particularly, to a structure and method of forming tunable voltage margin access diodes using layers of mixed ionic-electronic conduction (MIEC) materials.

In order to increase the density of memory technologies (both volatile and nonvolatile), a crosspoint design is typically preferred. In such an optimized design, the wordlines and bitlines (hereafter referred to as memory lines) run at minimum pitch=2F, where F refers to the lithographic minimum feature size (for example, 32 nm), and storage elements are placed between these perpendicularly oriented memory lines at their crosspoints.

Two device components are needed at the crosspoint of the memory lines: (a) a memory element and (b) a rectifying diode or access device (AD). The memory element refers to an element that is used to store data/information. Many options exist here, including, for example, phase change memory (PCM), MRAM, Resistive RAM (RRAM), solid electrolyte memory, FeRAM, etc. The rectifying element or AD is needed because a transistor is usually not provided at every crosspoint, so a device is needed to rectify current (i.e., exhibit nonlinearity). This ensures that the memory cells that lie on unselected wordlines and bitlines are not inadvertently programmed or shorted to each other and do not leak any significant amount of current.

The quality of single-crystal silicon p-n and Schottky diodes that can be fabricated in middle-of-line (MOL) or back end of line (BEOL) lower temperature processes is typically very low since they have to be made in amorphous or polycrystalline silicon that has much lower mobility. This may prevent the use of p-n junctions in either single-crystal silicon or other silicon materials as rectifiers for high-current memory elements (especially in 3D applications).

Instead of using single-crystal silicon p-n and Schottky diodes as ADs at the crosspoint of the memory lines, solid electrolyte (SE) diodes may be used. The advantage of this approach is the high ON/OFF ratio, as the SE can provide very high currents in the ON state (since it has a metallic filament that bridges the two electrodes) and very low OFF currents. However, disadvantages with this approach include: the need for an explicit erase step to erase the filament, wherein such an erase step can be quite slow (for example, hundreds of microseconds are needed to erase a thick filament); the low reliability/endurance of the SE element during high current programming; and the very low OFF current actually being near or below a noise floor current in some devices.

SUMMARY

According to an embodiment, a method of forming an access diode having a tunable voltage margin is disclosed. The method may include: forming a mixed ionic-electronic conduction (MIEC) layer on a substrate, the MIEC layer including one or more individual layers of MoS2; doping the MIEC layer with a conductive defect dopant; forming a first electrode on the MIEC layer; and forming a second electrode on the MIEC layer, the second electrode separated from the first electrode by a lateral portion of the MIEC layer.

According to another embodiment, a method of tuning a voltage margin of an access diode is disclosed. The method may include: adjusting a bandgap of the access diode by varying a number of layers of a mixed electronic-ionic conduction (MIEC) material used to electrically connect a first electrode and a second electrode; and adjusting defect energy and effective mass of the access diode by doping the MIEC material with a conductive defect dopant.

According to another embodiment, an access diode structure having a tunable voltage margin is disclosed. The structure may include: a mixed electronic-ionic conduction (MIEC) layer on a substrate, the MIEC layer including one or more individual layers of MoS2; a conductive defect dopant in a lattice structure of the MIEC layer; a first electrode on the MIEC layer; and a second electrode on the MIEC layer, the second electrode separated from the first electrode by a lateral portion of the MIEC layer.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

The following detailed description, given by way of example and not intended to limit the invention solely thereto, will best be appreciated in conjunction with the accompanying drawings, in which not all structures may be shown.

FIG. 1 is a cross section view of a structure, including a substrate, according to an embodiment of the present invention.

FIG. 2 is a cross section view illustration forming a MIEC layer on the substrate, according to an embodiment of the present invention.

FIG. 3 is a cross section view illustrating forming one or more electrodes on the MIEC layer, according to an embodiment of the present invention.

FIG. 4 is a graphical representation illustrating the density of states (DOS) and different bandgaps of the MIEC diode with different MIEC layers, according to embodiments of the present invention.

The drawings are not necessarily to scale. The drawings are merely schematic representations, not intended to portray specific parameters of the invention. The drawings are intended to depict only typical embodiments of the invention. In the drawings, like numbering represents like elements.

DETAILED DESCRIPTION

Detailed embodiments of the claimed structures and methods are disclosed herein; however, it can be understood that the disclosed embodiments are merely illustrative of the claimed structures and methods that may be embodied in various forms. This invention may, however, be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of this invention to those skilled in the art.

For purposes of the description hereinafter, the terms “upper”, “lower”, “right”, “left”, “vertical”, “horizontal”, “top”, “bottom”, and derivatives thereof shall relate to the disclosed structures and methods, as oriented in the drawing figures. It will be understood that when an element such as a layer, region, or substrate is referred to as being “on”, “over”, “beneath”, “below”, or “under” another element, it may be present on or below the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on”, “directly over”, “directly beneath”, “directly below”, or “directly contacting” another element, there may be no intervening elements present. Furthermore, the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

In the interest of not obscuring the presentation of embodiments of the present invention, in the following detailed description, some processing steps or operations that are known in the art may have been combined together for presentation and for illustration purposes and in some instances may have not been described in detail. In other instances, some processing steps or operations that are known in the art may not be described at all. It should be understood that the following description is rather focused on the distinctive features or elements of various embodiments of the present invention.

The present invention relates generally to high current density access devices (ADs), and more particularly, to a structure and method of forming tunable voltage margin access diodes in phase change memory (PCM) blocks using layers of copper-containing mixed ionic-electronic conduction (MIEC) materials. A MIEC diode is a two terminal diode device containing a solid electrolyte (SE) material in which both electron/hole carriers and the activated dopant ion (e.g., Frenkel-pair defects) drift in an applied electric field and contribute to the total current. MIEC-based ADs may offer the large ON/OFF ratios, a high voltage margin V_(m) (over which current <10 nA), and ultra-low leakage (<10 pA) needed to enable large arrays, as well as the high current densities needed for PCM and the fully bipolar operation needed for high-performance RRAM.

Embodiments of the present invention may use layers MIEC material to form an access device that can supply high current-densities and operate reliably while being fabricated at temperatures that are compatible with standard BEOL processing. By varying the deposition technique and amount of MIEC material used, the voltage margin (i.e. the voltage at which the device turns on and the current is above the noise floor) of the access device may be tuned to specific operating conditions of different memory devices. Methods by which to fabricate MIEC-based ADs having a tunable voltage margin are described in detail below with reference to FIGS. 1-4.

Referring now to FIG. 1, a cross section view of a structure 100 is shown. The structure 100 may include a substrate 102. The substrate 102 may be a bulk semiconductor substrate or a semiconductor on insulator (SOI) substrate. The substrate 102 may be made from any of several known semiconductor materials such as, for example, silicon, germanium, silicon-germanium alloy, carbon-doped silicon, carbon-doped silicon-germanium alloy, and compound (e.g. III-V and II-VI) semiconductor materials. Non-limiting examples of compound semiconductor materials include gallium arsenide, indium arsenide, and indium phosphide. In a preferred embodiment, the substrate 102 may be composed of silicon. The substrate 102 may be approximately, but is not limited to, several hundred microns thick. In an embodiment, the substrate 102 may have a thickness ranging from approximately 0.5 mm to approximately 1.5 mm.

Referring now to FIG. 2, a cross section view illustration forming a MIEC layer 202 on the substrate 102 is shown. In an embodiment, the MIEC layer 202 may be composed of molybdenum disulfide (MoS₂). MoS₂ is a semiconductor material made of layers that are weakly coupled by van der Waals forces. A layer is made of three atomic planes that are strongly bonded to each other: two hexagonal planes of sulfur atoms separated by one hexagonal plane of molybdenum atoms, with each molybdenum atom covalently bonded to six sulfur atoms in the adjacent planes. When present in layers, the sulfur atoms of one layer may be separated from the molybdenum atoms of an adjacent layer by approximately 3.46 angstroms. In an embodiment, the MIEC layer 202 may be doped with interstitial or substitutional defect atoms, such as copper (Cu) or chromium (Cr). The MIEC layer 202 may be doped with the defect atoms by conventional techniques, such as, for example, epitaxial doping, sputtering, vapor-phase epitaxy, chemical vapor deposition, diffusion, and ion implantation. In an embodiment, the defect atoms may be present in the MIEC layer 202 at a concentration ranging from approximately 1% to approximately 8%.

By varying the thickness and number of layers of MoS₂ in the MIEC layer 202, multiple parameters of the MIEC layer 202, such as bandgap (eV), defect energy (eV), voltage margin (V_(m)), and effective mass (m_(o)-hole), may be tuned based on the desired application. In an embodiment, the MIEC layer 202 may be composed of a single layer of MoS₂ doped with Cu. The single layer of MoS₂ may be formed using conventional deposition techniques, such as, for example, mechanical and chemical exfoliation, thin film sputtering, vapor-liquid-solid technique, molecular beam epitaxy, metal-organic chemical vapor deposition, or ion beam deposition. The single layer of MoS₂ may be doped with Cu using conventional deposition techniques, such as, for example, epitaxial doping, sputtering, vapor-phase-epitaxy, CVD, diffusion, or ion implantation. In an embodiment, the single layer of MoS₂ may have a thickness of approximately 6.5 angstroms.

In another embodiment, the MIEC layer 202 may be composed of two layers of MoS₂ doped with Cu arranged in a dual layer. In an embodiment, the sulfur atoms of one layer of MoS₂ may be separated from the copper atoms of the other layer of MoS2 by a distance of approximately 3.5 angstroms. This close proximity may result in physical interactions between the two layers of Cu doped MoS₂, resulting in the dual layer having different physical properties than the single layer of MoS₂, as illustrated below in Table 1. The two layers of MoS₂ may be formed using conventional deposition techniques, such as, for example, mechanical and chemical exfoliation, thin film sputtering, vapor-liquid-solid, molecular beam epitaxy, metal-organic chemical vapor deposition (MOCVD), or ion beam deposition. The two layers of MoS₂ may be doped with Cu using conventional doping techniques, such as, for example, epitaxial doping, sputtering, vapor-phase epitaxy, molecular beam epitaxy, CVD, MOCVD, diffusion, or ion implantation. In an embodiment, the two layers of MoS₂ may have a thickness ranging from approximately 1 nm to approximately 1.5 nm.

In another embodiment, the MIEC layer 202 may be composed of three or more layers of MoS₂ (i.e., bulk MoS₂) doped with Cu. The bulk MoS₂ may be formed using conventional deposition techniques, such as, for example, mechanical and chemical exfoliation, thin film sputtering, vapor-liquid-solid technique, molecular beam epitaxy, MOCVD, or ball milling. The bulk MoS₂ may be doped with Cu using conventional doping techniques, such as, for example, epitaxial doping, sputtering, vapor-phase epitaxy, molecular beam epitaxy, CVD, MOCVD, diffusion, or ion implantation. In an embodiment, the bulk MoS₂ may have a thickness ranging from approximately 10 nm to approximately 1 μm.

In another embodiment, the MIEC layer 202 may be composed of one or more ribbons of MoS₂ doped with Cu. In an embodiment, the ribbons may be formed by cutting or shaving one or more sacrificial layers of MoS₂ (typically 1-3 layers) into a strip of material having a finite narrow width. The cutting and/or shaving process may include conventional lithography techniques, such as, for example, electron-beam lithography or ion-beam lithography. In another embodiment, the ribbons of MoS₂ may be formed by the chemical unzipping of MoS₂ nanotubes. The ribbons of MoS₂ may be doped with Cu, either before or after the cutting, shaving, or unzipped processes, using epitaxial doping, sputtering, vapor-phase epitaxy, molecular beam epitaxy, CVD, MOCVD, diffusion, or ion implantation. The ribbons of MoS₂ may have a thickness ranging from approximately 6 angstroms to approximately 20 angstroms depending on whether the ribbon is made from a single layer MoS₂ or multiple layers MoS₂. The ribbons of MoS₂ may have a width ranging from approximately 1 nm to approximately 20 nm.

Referring now to FIG. 3, a cross section view illustrating forming one or more electrodes 302 (hereinafter “electrodes”) on the MIEC layer 202 is shown. The electrodes 302 may be composed of a conductive material. In an embodiment, the electrodes may be composed of a metal, such as, for example, Cu, W, Ti, Pt, Al, or alloys thereof. The electrodes 302 may be formed using a conventional deposition process, such as, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), molecular beam deposition (MBD), pulsed laser deposition (PLD), liquid source misted chemical deposition (LSMCD), or plating.

In an embodiment, the one or more layers of MoS₂ in the MIEC layer 202 may extend vertically from an upper surface of the substrate 102. Current may flow horizontally between the electrodes 302 and through the MIEC layer 202, forming a MIEC diode 304. In an embodiment, the MIEC diode 304 may be used as an access diode in a Phase Change Memory (PCM) block.

Because of the variable thicknesses and composition of the MIEC layer 202, the voltage margin of the MIEC diode 304 may be tuned to fit specific needs. Voltage margin is defined as the range of voltage across the access device for which the current through it is always below 10 nA. For instance, if the current increases above 10 nA at −|V_(b)| volts on the negative side and at +|V_(a)| volts on the positive side of a curve that plots access device current versus voltage applied to the top electrode (with the bottom electrode grounded), then the voltage margin would be equal to |V_(a)|±|V_(b)|.

As shown in Table 1, the voltage margin can be varied significantly depending on the composition and thickness of the MIEC layer 202. The following data is based on an ab-initio simulation (i.e., a quantum mechanical parameter-free simulation using density functional theory (DFT) where many body interactions are taken into account to solve many-particle Schrodinger equations) of a MIEC diode 304 having various MIEC layers 202. The ab-initio simulation allows for the estimation of material properties of electronic structures, such as band gap, effective mass, thermal properties, magnetic properties, etc., as shown below.

TABLE 1 Material Properties of MIEC Diodes with Different MIEC Layers MIEC Defect Voltage Effective Layer Bandgap Energy Margin Mass (MoS₂—Cu) (eV) (eV) (V_(m)) (m_(o)-hole) Single Layer 1.8 0.8 1.28 0.82 Two Layers 1.4 1.15 0.84 0.85 Bulk 1.2 1.0 0.76 0.87

Referring now to FIG. 4, a graphical representation illustrating the density of states (DOS) and different bandgaps of the MIEC diode 304 with different MIEC layers 202 is shown. The graph shows the different DOS (i.e., the number of quantum states available per energy interval) at different energy levels of the MIEC diode 304. A high DOS at a specific energy level means that there are many states available for occupation. As shown in FIG. 4, the different MIEC layers 202, having different band gaps, result in different DOS at different energy levels, which can enable the tuning of the MIEC diode 304 based on desired parameters.

The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiment, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein. 

1. A method of forming an access diode having a tunable voltage margin comprising: forming a mixed ionic-electronic conduction (MIEC) layer on a substrate, the MIEC layer comprising one or more individual layers of MoS₂; doping the MIEC layer with a conductive defect dopant; forming a first electrode on the MIEC layer; and forming a second electrode on the MIEC layer, the second electrode separated from the first electrode by a lateral portion of the MIEC layer, wherein the doping the MIEC layer with the conductive defect dopant comprises: interstitial or substitutional doping a lattice structure of the MIEC layer with Cu or Cr.
 2. The method of claim 1, wherein forming the MIEC layer on the substrate comprises: forming a single layer of MoS₂ on the substrate.
 3. The method of claim 1, wherein forming the MIEC layer on the substrate comprises: forming a dual layer of MoS₂ on the substrate, the dual layer of MoS₂ comprising a first layer of MoS₂ and a second layer of MoS₂ separated from one another by approximately 3.5 angstroms.
 4. The method of claim 1, wherein forming the MIEC layer on the substrate comprises: forming a bulk layer of MoS₂ on the substrate, the bulk layer of MoS₂ comprising three or more layers of MoS₂.
 5. The method of claim 1, wherein forming the MIEC layer on the substrate comprises: depositing one or more ribbons of MoS₂ on the substrate, the one or more ribbons of MoS₂ comprising a strip of material having a finite narrow width ranging from approximately 1 nm to approximately 20 nm.
 6. The method of claim 5, wherein depositing the one or more ribbons of MoS₂ on the substrate comprises: cutting or shaving one or more sacrificial layers of MoS₂ into strips.
 7. The method of claim 5, wherein depositing the one or more ribbons of MoS₂ on the substrate comprises: chemically unzipping one or more MoS₂ nanotubes.
 8. (canceled)
 9. A method of tuning a voltage margin of an access diode comprising: adjusting a bandgap of the access diode by varying a number of layers of a mixed electronic-ionic conduction (MIEC) material used to electrically connect a first electrode and a second electrode; and adjusting defect energy and effective mass of the access diode by doping the MIEC material with a conductive defect dopant, wherein doping the MIEC material with the conductive defect dopant comprises: interstitial or substitutional doping a lattice structure of the MIEC material with Cu or Cr.
 10. The method of claim 9, wherein varying the number of layers of MIEC material comprises: forming a single layer of MoS₂ on a substrate.
 11. The method of claim 9, wherein varying the number of layers of MIEC material comprises: forming a dual layer of MoS₂ on a substrate, the dual layer of MoS₂ comprising a first layer of MoS₂ and a second layer of MoS₂ separated from one another by approximately 3.5 angstroms.
 12. The method of claim 9, wherein varying the number of layers of MIEC material comprises: forming a bulk layer of MoS₂ on a substrate, the bulk layer of MoS₂ comprising three or more layers of MoS₂.
 13. The method of claim 9, wherein varying the number of layers of MIEC material comprises: depositing one or more ribbons of MoS₂ on a substrate, the one or more ribbons of MoS₂ comprising a strip of material having a finite narrow width ranging from approximately 1 nm to approximately 20 nm.
 14. (canceled)
 15. An access diode structure having a tunable voltage margin comprising: a mixed electronic-ionic conduction (MIEC) layer on a substrate, the MIEC layer comprising one or more individual layers of MoS₂; a conductive defect dopant in a lattice structure of the MIEC layer; a first electrode on the MIEC layer; and a second electrode on the MIEC layer, the second electrode separated from the first electrode by a lateral portion of the MIEC layer, wherein the conductive defect dopant comprises Cu or Cr.
 16. The access diode structure of claim 15, wherein the MIEC layer comprises: a single layer of MoS₂ on the substrate.
 17. The access diode structure of claim 15, wherein the MIEC layer comprises: a dual layer of MoS₂ on a substrate, the dual layer of MoS₂ comprising a first layer of MoS₂ and a second layer of MoS₂ separated from one another by approximately 3.5 angstroms.
 18. The access diode structure of claim 15, wherein the MIEC layer comprises: a bulk layer of MoS₂ on the substrate, the bulk layer of MoS₂ comprising three or more layers of MoS₂.
 19. The access diode structure of claim 15, wherein the MIEC layer comprises: one or more ribbons of MoS₂ on a substrate, the one or more ribbons of MoS₂ comprising a strip of material having a finite narrow width ranging from approximately 1 nm to approximately 20 nm.
 20. (canceled) 